A BICMOS IC fabrication process for fabricating both bipolar and CMOS transistor structures recently in use at National Semiconductor Corporation, South Portland, Me. 04106 is summarized in TABLE I showing the overall BICMOS mask sequence. Further description of the BICMOS process mask sequences is also found in the Murray J. Robinson, Christopher C. Joyce, and Timwah Luk U.S. patent application Ser. No. 655,676 filed Feb. 14, 1991 for BIPOLAR TRANSISTOR STRUCTURE AND BICMOS IC FABRICATION PROCESS, the Robinson, Joyce, and Luk U.S. patent application Ser. No. 803,214 filed Dec. 6, 1991 for SCHOTTKY DIODE STRUCTURE AND FABRICATION PROCESS, and the Donald J. Desbiens U.S. patent application Ser. No. 840,390 filed Feb. 24, 1992 for WAFER LEVEL RELIABILITY CONTACT TEST STRUCTURE.
TABLE I ______________________________________ BICMOS WAFER FABRICATION MASK SEQUENCES Mask No. Mask Function ______________________________________ 1.0 Buried Collector Layer (BCL) Mask 2.0 Retro NWELL Mask and Retro SEC Mask 3.0 Retro PWELL Mask and Channel Stop (CHST) Mask 4.0 Isolation Oxide (ISOX) Mask 5.0 Sink Definition Mask & ISOX Gettering Mask 6.0 CMOS Active Area Definition Mask (Field Oxide Mask) & Collector Base Surface Spacer (CBSS) Definition Mask 7.0 Active Strip Mask 8.0 Poly Gate Definition Mask 9.0 Base Definition Mask 10.0 Nitride Etch Mask and Collector Base & Emitter Contact Definition Mask 11.0 Emitter Definition Mask & Collector Sink Contact Mask (Self-Aligned Transistor Mask) 12.0 N+S/D Source/Drain Mask (NMOS) 13.0 P+S/D Source/Drain Mask (PMOS) 14.0 CMOS Contact Definition Mask 15.0 METAL 1 (M1) Definition Mask 16.0 VIA Mask (Inter Layer Dielectric Mask) 17.0 METAL 2 (M2) Definition Mask 18.0 Passivation Mask and Bond Pad Definition Mask ______________________________________
A buried collector layer BCL for bipolar transistors is formed typically in a P type substrate using the 1.0 BCL mask, etch, and N+ type dopant material introduction sequence at the beginning of the BICMOS wafer fabrication process. Relatively slow diffusing N type antimony atoms are implanted in the P type substrate to an N+ concentration through an initial oxide layer. A new photoresist layer is then deposited to form the 2.0 retro NWELL mask. The 2.0 retro NWELL mask sequence provides the retro NWELL definition mask, etch, and N+ type impurity ion introduction sequence through an NWELL opening for the CMOS/PMOS transistor structures. At the same time, it also provides a subemitter collector (SEC) region definition mask, etch, and N+ type impurity ion introduction sequence through an SEC opening for the bipolar transistor structures. By way of example, the SEC opening in the 2.0 retro NWELL mask is formed with a horizontal area of approximately 10% and preferably in the range of 10% to 20% of the horizontal cross section area of the BCL. Relatively fast diffusing phosphorous atoms are implanted to an N+ concentration level through the 2.0 mask. Phosphorous atoms are used for the N+ concentration implant of the SEC and NWELL regions for faster up diffusion during subsequent annealing steps as hereafter described to provide retrograde concentrations extending into the subsequently deposited epitaxial layer EPI.
The 3.0 retro PWELL mask, etch, and P+ type dopant material introduction sequence or 3.0 retro PWELL mask sequence is used for defining and introducing the retro PWELL region of the CMOS/NMOS transistor structures and the channel stop regions CHST adjacent to the bipolar transistor structures. Boron atoms are implanted to a P+ concentration level in the PWELL and CHST regions. A single crystal epitaxial layer EPI of lightly doped N- type silicon is then deposited uniformly over the BICMOS IC structure in a blanket epitaxial deposition without a mask. An epitaxial oxide layer EPIOX and a first chemical vapor deposition CVD nitride layer are formed over the EPI.
Isolation oxide regions are established around the bipolar transistor structures using the 4.0 isolation oxide mask, etch and isolation oxide grow sequence. The collector sink region CS is defined by introducing an N+ concentration of phosphorous atoms using the 5.0 sink definition mask, etch and N+ type impurity ion introduction sequence. The 5.0 sink definition mask is also formed for introducing phosphorous atoms as a gettering agent in the isolation oxide regions ISOX. A second uniform CVD nitride layer is deposited in a blanket chemical vapor deposition across the BICMOS structure.
The 6.0 Active Area Definition Mask or Active Mask is formed for etching the second CVD nitride layer and defining the active regions of the CMOS transistor structure. The openings in the 6.0 photoresist active mask expose the framing field oxide regions FOX for framing and isolating the PMOS and NMOS transistor structures during the subsequent field oxide grow oxidation step.
At the same time the 6.0 active mask, etch and field oxide grow sequence also functions as the collector base surface spacer region CBSS definition mask, etch, and CBSS oxide grow sequence for the bipolar transistor structures. The 6.0 photoresist active area definition mask functioning as a CBSS mask also exposes the surface area between the collector and base of bipolar transistors for the CBSS. In the subsequent field oxidation step, the collector base surface spacer region CBSS between the collector and base of bipolar transistors is formed from field oxide rather than isolation oxide.
In the 7.0 active strip mask, etch, CMOS transistor voltage threshold (V.sub.T) adjust, and gate oxide grow sequence steps, the second CVD nitride layer is stripped except over the bipolar transistor structures. In a series of subsequent steps the active areas of the CMOS transistor structures are opened to expose the epitaxial silicon as hereafter described in detail with reference to FIGS. 1-6. The gate oxide layer GOX is grown typically in a slow high temperature dry oxide process.
Gate material polysilicon (POLY) is subsequently deposited uniformly in one or two layers. The 8.0 poly gate definition mask and etch steps define the gates for CMOS transistors using a photoresist layer and photolithographic stepper sequence followed by etching the poly layer and leaving behind the poly gates over the gate oxide layer. A thin oxide layer referred to as a sealing oxide or spacer oxide is grown over the poly gates. A lightly doped source and drain N type dopant material introduction sequence such as an N- phosphorus implant initiates preparation of the profile of source and drain regions of CMOS transistors.
The 9.0 base definition mask, etch and introduction sequence is used for defining and introducing P type boron atoms for the base of the bipolar transistor structure. The base is implanted through the second CVD nitride layer which functions as a base implant screen. The 10.0 nitride etch mask provides a collector, base and emitter contact definition mask using the second CVD nitride layer and forming a self-aligned transistor (SAT) CVD nitride mask over the bipolar transistor structure. The epitaxial oxide layer EPIOX remains over the bipolar transistor structure with the CVD nitride SAT mask defining the collector, base and emitter contacts.
The 11.0 emitter definition and collector sink introduction mask is constructed to utilize the underlying CVD nitride SAT mask over the bipolar transistor structure. The emitter and collector sink regions are implanted to an N+ concentration level with N type arsenic atoms. While previous annealing steps have begun development of the retrograde concentration upward from the PWELL, NWELL, and the SEC region, the subsequent emitter annealing step following implant of the emitter and collector sink regions fully develops most of the retrograde concentration profile of dopant atoms.
The 12.0 N+S/D source/drain mask, etch and N+ type impurity ion introduction sequence for the NMOS transistor elements provides an N+ phosphorus implant over the previous lightly doped drain N- phosphorus implant in the source and drain regions. The combination of the N- and N+ phosphorous implants develops a profiled lightly doped drain for the NMOS transistor element of the CMOS transistor pairs. The 13.0 P+S/D source/drain mask, etch and P+ type dopant material introduction sequence is used for implanting the source and drain regions of the PMOS transistor structure.
Following the source/drain mask, etch and dopant material introduction sequences for the NMOS and PMOS transistor elements of the CMOS transistor structure, a blanket low temperature oxide layer LTO is deposited over the BICMOS structure. The 14.0 CMOS contact definition mask and etch sequence removes the LTO over the CMOS metal contact areas and over the bipolar transistor structure. The SAT CVD nitride mask on the bipolar transistor structures is finally etched for defining the bipolar transistor metal contact areas. In subsequent mask steps the first metal layer is deposited and then selectively etched using the 15.0 Metal 1 or M1 definition mask and etch sequence for defining M1 metal contacts, followed by blanket deposition of an interlayer dielectric (ILD). The ILD is masked and etched using the 16.0 VIA mask to define the locations of interlayer contacts followed by blanket deposition of the second metal layer. The 17.0 Metal 2 or M2, definition mask and etch sequence defines the M2 metal contacts. A passivation layer such as a PECVD layer is deposited over the BICMOS structure and the final 18.0 passivation mask and etch sequence cuts holes in the PECVD layer for bond pads.
The standard CMOS transistor 7.0 active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence of steps is described in further detail with reference to FIGS. 1-6. The CMOS transistor active area strip mask is referred to simply as the active strip mask and is designated 7.0 MASK in FIG. 1. The 7.0 MASK is a photoresist mask which exposes the active area of CMOS transistors for etching and stripping the second chemical vapor deposition nitride layer CVDSIN and the underlying epitaxial oxide layer EPIOX. As shown in FIG. 1, an NWELL or PWELL underlies the active area according to whether the CMOS transistor is a PMOS transistor or NMOS transistor respectively. The NWELL or PWELL forms a retrograde concentration of N type or P type dopant material in the epitaxial layer EPI formed over the substrate SUB of, for example, P type silicon. In a BICMOS process, the CVD nitride layer CVDSIN is the second nitride layer deposited over the EPIOX of the CMOS transistor active areas. It is formed prior to the 6.0 active area definition or field oxide definition mask, etch and field oxide grow sequence. The field oxide regions FOX frame the active areas of the CMOS transistors.
According to a conventional CMOS IC fabrication process for preparing CMOS transistors, the nitride layer CVDSIN is typically formed with a thickness in the range of 1,200A-1500A (angstrom units). The nitride layer is formed by a uniform chemical vapor deposition across the CMOS wafer prior to the CMOS active area definition mask, etch and field oxide grow sequence. In the active area definition mask and etch sequence the epitaxial layer EPI is exposed around the CMOS transistor active areas for growing the field oxide FOX that frames and isolates the respective PMOS and NMOS transistors. The nitride layer CVDSIN is formed over the epitaxial oxide layer EPIOX of the CMOS transistor active areas. The EPIOX was formed after epitaxial deposition of the EPI layer following the NWELL and PWELL definition mask, etch and dopant material introduction sequences. The EPIOX is typically formed to a thickness of, for example 400A to 500A. The ratio of thickness of the respective layers CVDSIN/EPIOX is therefore conventionally in the range of 3/1 to 4/1.
In a pure CMOS IC fabrication process, a photoresist mask is typically not required for the following active strip, voltage threshold V.sub.T adjust, and gate oxide grow sequence illustrated in FIGS. 1-6. This is because the 7.0 MASK is not required to protect the nitride layer CVDSIN over adjacent bipolar transistor active areas. For integration of the CMOS transistor preparation steps into a BICMOS IC fabrication process, the 7.0 active strip mask sequence is required to protect bipolar transistor active areas. Also, in a full BICMOS process, the nitride layer CVDSIN illustrated in FIG. 1 is in fact the second CVD nitride layer. A first CVD nitride layer is required for the 4.0 isolation oxide mask, etch and ISOX grow sequence and this first CVD nitride layer is stripped prior to other bipolar steps. The second CVD nitride layer CVDSIN, illustrated in FIG. 1 is conventionally deposited to a thickness, of for example 1275A over EPIOX in the range of approximately 400A as in the case of conventional CMOS transistor preparation steps. The ratio of CVDSIN/EPIOX therefore conventionally falls in the range of 3/1 to 4/1 for both CMOS and BICMOS standard fabrication processes.
As shown in FIG. 2, the nitride layer CVDSIN is stripped from the CMOS transistor active areas in a nitride etch exposing the EPIOX layer. The epitaxial oxide layer EPIOX, also known as the pad oxide layer or PADOX layer is then removed in an oxide etch or dip. Following stripping of the CVDSIN and EPIOX layers from the CMOS transistor active areas, the photoresist 7.0 MASK is also stripped exposing the second nitride layer CVDSIN over bipolar transistor active areas at the same time that the epitaxial silicon EPI is exposed over the respective NWELL and PWELL active areas of the PMOS and NMOS transistors.
According to the conventional gate oxide sequence that begins with the 7.0 active strip mask and etch sequence, a sacrificial oxide layer SACOX, also known as a pregate oxide layer, is grown in an oxide grow thermal cycle over the exposed EPI of the NWELLs and PWELLs of PMOS and NMOS transistors. The SACOX grow thermal cycle is followed by a blanket implant of boron ions as illustrated in FIG. 4 for adjusting the voltage threshold V.sub.T of the CMOS transistors.
The sacrificial oxide layer SACOX is typically grown to a thickness of, for example, 400A. The SACOX growth followed by stripping is intended to provide an extremely clean EPI surface for tight control of the gate oxide thickness grown in subsequent steps. The SACOX layer also provides a screen oxide layer for the V.sub.T adjust implant and is then stripped as illustrated in FIG. 5. A thin gate oxide layer GOX is grown to a thickness of, for example, 150A in a tightly controlled slow growth dry oxygen process at high temperature. For example, the dry oxide GOX is typically grown at a temperature in the range of 900.degree. C. to 1000.degree. C. As used herein, the reference to "high temperature" or "relatively high temperature" for the thermal cycles of the fabrication steps generally refers to a temperature of 900.degree. C. or greater, while a temperature indicated to be at "relatively low temperature" generally refers to a temperature below 900.degree. C. A dry oxide GOX thermal cycle is generally required for slow growth to achieve the tightly controlled critical thickness of, for example, 150.degree. A for the gate oxide layer. The dry oxide process in turn requires the relatively high temperatures in the range of 900.degree. to 1000.degree. C.
A number of problems are associated with the standard active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence illustrated in FIGS. 1-6. First, the inventors have determined that the conventional nitride layer CVDSIN in the range of 1200A to 1500A formed over the relatively thin EPIOX layer of 400A to 500A introduces substantial differential stresses at the silicon/silicon dioxide (Si/SiO.sub.2) interfaces particularly in the bipolar transistor structures. The relatively thick CVD nitride layer stresses induce crystal lattice defects in the epitaxial silicon particularly in the vicinity of nitride and silicon dioxide interfaces. Such crystal lattice defects or holes become gettering centers for contaminants which change the conductivity specifications of the semiconductor material. This effect is increased by the subsequent thermal cycles and high temperatures of the conventional gate oxide sequence as silicon crystal lattice defects propagate into the substrate under thermal stress.
Such differential stress and thermal stress induced silicon defects cause substantial reduction in the yield of acceptable dies from the BICMOS wafer. Such defects are manifested in collector to base leakage current flow along lattice defect paths across the collector base junction. Bipolar leakage current exceeding specifications may reduce the yield of acceptable dies on a BICMOS wafer by 20% and in the extreme to a yield as little as 5%.
A second disadvantage of the conventional gate oxide sequence set forth in FIGS. 1-6 is that the SACOX loop or SACOX cycle causes substantial nonuniformity in the nitride layer CVDSIN over bipolar transistor structures. Growing the sacrificial oxide layer and subsequently stripping the sacrificial oxide layer following the V adjust implant takes place while the nitride layer CVDSIN is exposed over the bipolar transistor structure. The impacted nitride layer provides the implant screen layer for the subsequent 9.0 base definition mask, etch and P type dopant material introduction sequence. The selected thickness of the CVD nitride layer establishes the .beta. (amplification) for the bipolar transistors and a uniform nitride layer is essential to maintaining the .beta. specification across the wafer. The resulting nonuniformities in the nitride layer CVDSIN across the bipolar transistors may cause unacceptable variation in the .beta. of bipolar transistors.
A third disadvantage of the prior art gate oxide sequence of FIGS. 1-6 is the excessive manufacturing cycle time required by the gate oxide process of FIGS. 1-6 and related BICMOS IC fabrication steps impacted by the gate oxide sequence. For example, the SACOX grow and strip loop adds an oxide grow thermal cycle at relatively high temperature. However it is essential in order to achieve acceptable reliability for the gate oxide layer grown in a slow dry oxide process. That is, it is essential to assure the extremely clean epitaxial silicon over the active area for tight control of gate oxide specifications. Furthermore, the dry oxide growth is a slow process believed necessary for tight control of gate oxide thickness. However it results in a prolonged thermal cycle at high temperatures. A related fourth disadvantage of the conventional gate oxide sequence is the number of thermal cycles and prolonged thermal cycles at high temperatures which increase thermal stress and propagation of stress induced silicon crystal defects.
A fifth disadvantage is that annealing of the gate oxide layer occurs as an integral part of the gate oxide process loop at the end of the sequence with a short annealing ramp in temperature in the range for example of 900.degree. C. to 950.degree. C. This abbreviated annealing step cannot achieve the full potential of annealing densification of the gate oxide layer to provide the maximum potential of gate oxide integrity and reliability.
A sixth disadvantage of the conventional gate oxide sequence is that the process steps result in excessive loss of nitride from the nitride layer CVDSIN and excessive loss of field oxide at the field oxide regions. These losses occur at two steps of the BICMOS process and require compensating increase in thickness of the CVDSIN layer and the field oxide region when initially formed. As previously noted, the SACOX grow and strip cycle produces nonuniform topography of the CVD nitride layer over bipolar transistors. It also produces an absolute loss of nitride from the CVD nitride layer impairing the .beta. specification for bipolar transistors. Of greater significance, the nitride loss from the nitride layer CVDSIN during the SACOX cycle removes a thin layer of oxidized nitride or nitrox formed over the nitride layer during the field oxide grow sequence. The stripping of the sacrificial oxide SACOX also removes the nitrox layer. The inventors determined that this nitrox layer provides significant protection for the underlying nitride layer CVDSIN during the subsequent polyetch.
The second process step at which nitride loss and field oxide loss occurs is during the poly gate definition mask and etch sequence. Following the 7.0 active strip mask, etch, V.sub.T, adjust, and gate oxide grow sequence, a uniform polycrystalline silicon layer is deposited over the wafer. The uniform polysilicon layer is then patterned and etched in the polygate definition mask and etch sequence leaving behind the polygates over the CMOS transistor active areas. An overetch is required to assure removal of the polycrystalline silicon at locations outside the polygates resulting in nonuniform loss of, for example, as much as 100A to 200A nitride. The combined losses from the SACOX cycle and polyetch may be as great as 20% of the nitride layer CVDSIN. Similarly the loss in field oxide may be as great as 900A. As a result greater CVD nitride must be afforded at the outset to maintain the .beta. of bipolar transistors, and greater field oxide thickness is required to meet field oxide specifications.